The present invention relates to control and monitoring of multiplexed communications networks and, more particularly to multiplexing data and power transmission through a single conductor of a common bus.
By way of example, various systems for transmitting data produced by a large number of subscribers from one location to another are known, as described in U.S. Pat. No. 4,059,729 to Eddy et al. Typically time division multiplexing is used to combine data into a multiplexed data stream and transmitted over a transmission network, including telephone lines, radio transmission equipment, and the like. As further illustrated by way of example, bus lines between peripheral devices and a central control transmit data for controlling pulsed data information through various desirable conductive paths, as described in U.S. Pat. No. 4,105,871 to Ely et al. Such multiplexing systems, and those known in the art, typically require separate wires for power, synchronizing clock pulses, and data. Other methods of transferring data with power require the use of a radio frequency carrier, which requires complex filtering and circuitry for the modulation and demodulation of the data. Further, it is well known that the number of devices that can typically be connected to a multiplexed bus is undesirably limited.
There is a need for providing a multiplexed bus system of transmitting and receiving data with a minimal number of components, which will dramatically reduce the cost of the multiplex system. Further, there is a need for such a system that will support many hundreds of transceivers for communicating with input and output devices.
In view of the foregoing background, it is therefore an object of the present invention to provide for the multiplexing of data and power to transceivers communicating on a common bus. It is further an object of the invention to provide such a multiplexing system that employs a minimum of components for reducing cost when compared to systems providing typical multiplexing functions.
These and other objects, advantages and features of the present invention are provided by a communications and control system comprising a bus having a signal wire, a transceiver electrically connected to the bus for transmitting and receiving an electrical signal through the signal wire, and a processor operable with the bus for controlling power and data delivered thereto. The controller provides the electrical signal to the transceiver through the signal wire as a pulsed waveform having a plurality of voltage pulses separated by a time slot, wherein power is delivered with each voltage pulse and absent during the time slot. Further, the controller operates to data to the transceiver through a pulse width modulation of the pulsed waveform, with the transceiver transmitting data to the signal wire of the bus during the time slot as a logical bit for reading by the controller. As a result, data is transmitted to the transceiver and received from the transceiver through the one signal wire of the bus through which the power for the transceiver is delivered.
A method aspect of the invention includes communicating and controlling a system through a single conductor by providing power to a single conductor as a voltage waveform having a pulsed operating voltage separated by a time slot wherein power is not applied to the bus during the time slot, pulse width modulating the waveform such that a first pulse width represents a logical one and a second pulse width represent a logical zero, and connecting a transceiver to the single conductor for receiving the voltage waveform therefrom for powering thereof and receiving data therefrom. Data from the transceiver is transmitted during the time slot as a logical bit. As a result, pulse width modulating the waveform transmits data to the transceiver and the logical bit data transmitted by the transceiver within the time slot can be received from the transceiver, with each being transmitted through the single conductor through which power is delivered to the transceiver.
In one embodiment, the width of the power pulse is compared to the width of the time slot, wherein a power pulse width equal to the time slot width represents a first logical bit value, and the power pulse width unequal to the time slot width represents a second logical bit value. Further, the transmitting and receiving of data is accomplished by transmitting a multiple bit scheme, wherein a single low bit indicates a start bit, transmitting a plurality of data bits following the start bit, and transmitting a final bit representative of one of a data bit and an address bit.